In a DRAM device which performs only burst read/write operation, in a write cycle or a read cycle performed every word line, a plurality bits of data are continuously read from or written to a memory cell array. Such a DRAM device can perform fast read and write operations, and is therefore suitable for a secondary cache memory of a MPU (Micro Processor Unit).
However, in a DRAM device it is necessary to precharge bit lines to a predetermined potential when the write/read cycle is started, because of the structure of the memory cells of the DRAM device. Therefore, it is usually impossible to continuously execute write or read cycles and to perform data input or output continuously over a plurality of write or read cycles. In order to perform continuous data input and/or output, a special device therefore is required.
On the other hand, there is known a SDRAM (Synchronous Dynamic Random Access Memory) device in which high speed data write/read operation can be performed in synchronism with an external control signal. In the SDRAM device, a memory cell array is divided into a plurality of banks, and the write/read operation is performed while switching between the banks. Also, in the banks not selected, the precharge operation is previously performed. Thereby, continuous data write/read operation can be performed.
However, even in the SDRAM device, it is impossible to perform continuous write/read operation within the same bank.
Here, an explanation will be made on the read/write operation within the same bank in the SDRAM device.
FIG. 10 is a block circuit diagram illustrating a schematic electrical structure of a SDRAM device having a memory cell array which comprises a plurality of banks. FIG. 11 is a timing diagram used for explaining a write operation of the SDRAM device of FIG. 10. FIG. 12 is a timing diagram used for explaining read operation of the SDRAM device of FIG. 10.
In the SDRAM device shown in FIG. 10, a memory cell array is divided into a plurality of memory banks, for example, a bank A and a bank B. A chip select signal *CS, a row address strobe signal *RAS, a column address strobe signal *CAS, and a write enable signal *WE supplied from external are decoded in a command decoder 101, and internal control signals for determining operation modes such as write/read operation, refresh operation and the like are produced and supplied to a control logic 102. Here, a symbol * designates logical inversion, and corresponds to an overline used in the drawings. In the control logic 102, timing of the internal control signals from the command decoder 101 is adjusted depending on information on latency of write/read operation and the like supplied from a mode register 103. The internal control signals whose timing is adjusted are supplied to various portions of the SDRAM device.
In response to the internal control signal or signals, a row address buffer and refresh counter block 104 supplies X (row) address for raising a potential of a word line to a row decoder 105. Also, in response to the internal control signal or signals, a column address buffer and burst counter block 106 supplies Y (column) address for raising a potential of bit lines to a column decoder 107. Thereby, in a selected bank A, for example, it becomes possible to perform a data write/read operation. In this case, in the row address buffer and refresh counter block 104, a word line to be refreshed is counted in response to a refresh command. Also, in the column address buffer and burst counter block 106, the number of data bits to be burst read/written is counted.
A sense amplifier block 108 amplifies an output data signal from each memory cell in a read operation to determine logical status of the output data. A data control circuit 109 controls the selection of data bus for the memory cell array and controls the selection of banks, in the write/read operation. A latch circuit 110 temporarily stores an input/output data for delivery thereof with an external circuit in response to an external control signal DQM. An input/output buffer 111 performs delivery of data with the external circuit. A clock generator 112 supplies clock signals for operation to various portions of the SDRAM device.
Operation of the SDRAIM device of FIG. 10 will be described in detail with reference to the drawings.
FIG. 11 shows waveforms of various portions of the SDRAM device of FIG. 10, when write operation is performed. As shown in FIG. 11, when data is written to the bank A, based on an active command supplied to the SDRAM device, a chip select signal *CS and a row address strobe signal *RAS become logically low potential level. Also, based on an address signal A11 among an address signals supplied to the SDRAM device, the bank A is selected. Based on an address signal A10 and based on address signals ADD (i.e., A9-A0), among the address signals supplied to the SDRAM device, X address XA0 is selected.
Then, in response to a write command, the chip select signal *CS and a column address strobe signal *CAS become logically low potential level (i.e., low). Also, based on the address signal A11, the bank A is selected, and, based on the address signals ADD (i.e., A9-A0), Y address YA0 is selected. Further, a write enable signal *WE becomes low and, in response thereto and when a word line WL is activated, data DQ including data D00, D01, D02 and D03 serially supplied is written as a burst to the bank A according to the Y address YA0 in order of D00, D01, D02 and D03.
Before starting the next write operation cycle, in response to a precharge command, the chip select signal *CS and the write enable signal *WE become low. Also, based on the address signal A11, the bank A is selected, and each bit line of the bank A is precharged. When write operation is to be performed continuously, a next X address XA1 is selected based on the address signal A10 and the address signals ADD, and a next Y address YA1 is selected based on the address signals ADD. Then, operation cycles similar to those mentioned above with respect to the X address XA0 and Y address YA0 are repeated.
FIG. 12 shows waveforms of various portions of the SDRAM device of FIG. 10, when read operation is performed. As shown in FIG. 12, when data is to be read from the bank A, based on an active command supplied to the SDRAM device, the chip select signal *CS and the row address strobe signal *RAS become logically low. Also, based on an address signal A11 among an address signals supplied to the SDRAM device, the bank A is selected. Based on an address signal A10 and based on address signals ADD (i.e., A9-A0), among the address signals supplied to the SDRAM device, X address XA0 is selected.
Then, in response to a read command, the chip select signal *CS and the column address strobe signal *CAS become low. Also, based on the address signal A11, the bank A is selected, and, based on the address signals ADD (i.e., A9-A0), Y address YA0 is selected. Further, when a word line WL is activated, data DQ, that is, data D00, D01, D02 and D03, is read out serially as a burst after a delay time of 3 clocks from the bank A according to the Y address YA0 in order of D00, D01, D02 and D03. The delay time of 3 clocks is determined depending on the information on latency supplied from the mode register 103 and corresponds to latency 3.
Before starting the next read operation cycle, in response to a precharge command, the chip select signal *CS and the write enable signal *WE become low. Also, based on the address signal A11, the bank A is selected, and each data line of the bank A is precharged. When read operation is to be performed continuously, a next X address XA1 is selected based on the address signal A10 and the address signals ADD, and a next Y address YA1 is selected based on the address signals ADD. Then, operation cycles similar to those mentioned above with respect to the X address XA0 and Y address YA0 are repeated.
As mentioned above, even in a SDRAM device having a bank structure, it was impossible to continuously perform write or read operation to or from addresses within the same bank, when write or read cycles continue. Similarly, in a DRAM device which does not have a bank structure, it was impossible to continuously perform write or read operation when write or read cycles continue.
If it is possible, in a DRAM device or in the same bank of a SDRAM device, to continuously perform write or read operation when write or read cycles continue, ability of a memory device can be enhanced and operation speed thereof can be greatly improved. However, such continuous write or read operation was impossible in a conventional DRAM device.